1. Field of the Invention
The invention generally relates to integrated circuits (ICs) and in particular to ICs incorporating dynamic or domino logic circuits.
2. Description of Related Art
A static CMOS gate is a fully complementary logic gate (with P and N devices configured to implement a desired logic function). A dynamic CMOS gate consists of an N-device logic structure having an output node precharged to V.sub.CC with a single clocked PMOS device and being conditionally discharged (evaluated) by a set of n-devices connected to V.sub.SS.
The clocked PMOS device has a gate connected to an input clock signal. When the clock input is active, the output node is "precharged" through the PMOS device to V.sub.CC. When the clock input is inactive, the output node is conditionally discharged (evaluated) through the N-devices to V.sub.SS. The set of N-devices implement the logic function.
Dynamic or domino logic units are referred to as being "dynamic" because operation of the unit is controlled dynamically by the input clock signal. The logic units are typically arranged in a plurality of stages, each having logic cells such as NAND gates, NOR gates, etc., with each stage separated by an inverting stage. With this arrangement, input signals applied to the first stage while the clock signal is active trigger operation of the remaining stages in sequence yielding a domino-like signal propagation effect within the logic unit--hence, the alternative name "domino" circuit.
One of the requirements for correct operation is that during the evaluate phase, the inputs to the N-device can only change from a non-active to an active state. Otherwise, the output could be corrupted, and there is no set of PMOS devices to pull it back up. This is done by providing inverting stages which are typically provided between each logic stage to facilitate proper precharging and evaluating of the individual logic units active during the precharge phase.
FIG. 1a illustrates a domino NAND gate cell 30. (A subsequent inverting state is not shown in the figure.) As can be seen, the NAND gate stage 30 includes a single PMOS device in combination with a pair of NMOS devices. Stage 32 is a sustainer which includes an inverter and a PMOS device. The sustainer offsets any charge leakage which might occur. The domino NAND gate of FIG. 1a is referred to as an "clocked" domino gate because the input clock signal is connected to an N-device in series with N-devices of the domino logic cell. The N-devices connected to clock prevents a power path between V.sub.CC and V.sub.SS during the precharge phase.
FIG. 1b illustrates a clocked domino NOR gate cell 50 and a subsequent sustainer stage 52.
In use, dynamic or domino logic units operate in two phases--a precharged phase and an evaluate phase. During the precharged phase, logic cells of the domino circuit are precharged. During the evaluate phase, input signals are applied to the inputs of each of the logic cells and the clock signals is activated. Depending upon the inputs, some of the logic cells of the domino circuit may need to discharge to pull the output line of the logic cell from high to low, thereby sinking current from the power supply. Other logic cells, however, within the domino circuit may not need to discharge and therefore will not sink significant current. Consider, for example, an AND circuit configured using domino circuitry. If the AND gate is precharged to provide a default output logic value of 1, and the input values are (0 0), (0 1) or (1 0), the AND gate will need to discharge the output line to pull the output line from logic 1 down to logic 0, thereby drawing significant power. If, however, the input values are (1 1), then the output line need not be discharged and it will retain its precharge value and no significant amount of power is drawn by the AND gate. Similar principles apply to other logic cells such as OR gates, NOR gates and NAND gates.
Thus, the actual power drawn within a domino circuit during each evaluation phase depends upon the input signals received during the evaluation phase. In designing domino circuits, it is generally assumed that individual binary value input signals will be distributed more or less at random over a period of time. Moreover, for a complex domino circuit incorporating numerous logic cells, it is generally assumed that about half of the cells will need to be discharged during each evaluation phase. Accordingly, the average power requirements for a complex domino circuit are typically determined by assuming that half of the logic cells of the circuit will need to discharge during each evaluation phase.
A domino logic unit has the advantage over conventional static CMOS logic units in that less overall circuit space is required than a static CMOS circuit because only a single PMOS device is required within each logic cell containing a set of NMOS devices. This represents a significant savings in circuit space over static CMOS circuits which require a PMOS device for each NMOS device. Domino CMOS circuits are also often significantly faster in operation than static CMOS circuits.
A significant disadvantage, however, of domino logic circuits over static CMOS logic circuits is that considerably more power is consumed by the domino device, despite the presence of the clocked PMOS transistors. A static CMOS circuit switches at most only once a cycle. Also, within a static CMOS logic circuit (having a path between V.sub.CC and V.sub.SS), power is only drawn by each logic cell (requiring a logic transition) only during the time it takes for the complimentary PMOS and NMOS devices of the cell to switch states which is typically very quick. A domino circuit consumes more power because it can switch twice every cycle, once during precharge and once during evaluate. Also, a domino circuit has a path between V.sub.CC and V.sub.SS for the period where the clock overlaps with the inputs resulting throughout power spent in that period.
Largely because of the generally higher power requirements of the domino circuit over a CMOS circuit, domino circuits are not widely employed within state of the art integrated circuits. Accordingly, it would be desirable to provide an improved method for implementing domino circuits which reduces the amount of power required by the domino circuit thereby yielding a domino circuit providing a more practical alternative to a CMOS circuit.